libLCS - A Logic Circuit Simulation library in C++


About || Examples || Tutorial and User Guide || Download || Installation


20th September 2006
libLCS-0.0.1 has been released. You can download it either by going through the Downloading libLCS page, or directly from the project page.


libLCS is a Logic Circuit Simulation library developed in 100% C++. It currently supports simulation of circuits with combinational logic. In the near future, it will also support sequential logic elements like clocks and FlipFlops. The ultimate aim of LCS is to support the functionality of the Verilog hardware description language while keeping the usage (and syntax) as intuitive as possible.

libLCS is still in very early stages of development and might contain a lot of bugs. Moreover, the API can get redone a lot of times before a beta version is released. However, you are encouraged to use it and report bugs and issues, if any, and help in making LCS popular ;-) and reliable. Use the above links to download/install/start using the library.

Like the library itself, this website is also under constant development. Hence, bear with any incovenience or lack of information. Do feel free to write in your comments to me. For bug reporting, feature requests, or any other comment regarding libLCS and its website, you can reach me at my id sivachandra_br. You can also use the links provided on the libLCS project page on


Copyright © 2006-2007 Siva Chandra

Generated on Wed Sep 20 00:49:12 2006 for libLCS by  doxygen 1.4.7