- A Logic Circuit Simulation Library in C++
19th August 2007
libLCS-0.0.57 has been released. You can download it either by going through the download page, or directly from the libLCS project page on sourceforge.net. A new utility class
The links to websites and documentation of older versions of libLCS can be found on the archives page.
libLCS is a library for Logic Circuit Simulation developed in 100% c++. The ultimate aim of LCS is to become a thorough hardware description library, matching the functionality of the Verilog hardware description language, while keeping the usage (and syntax) as intuitive as possible. Currently, it supports simulation of digital systems containing logic gates, flipflops, clock, user defined modules, and facilitates propogation delays, continuous assignments and dumping value changes into VCD files.
As libLCS is still in very early stages of development, it might contain bugs. Moreover, the API can get redone a lot of times before a beta version is released. However, you are encouraged to use it and report bugs and issues, if any, and help in making LCS popular ;-) and reliable. Use the above links to download, install, and start using the library. For bug reporting and feature/support requests, use the appropriate links provided on the libLCS project page on sourceforge.net. For problems with using the library, post your questions on the libLCS mailing list or public forums, links to which are again available on the project page. For easy access, I have also listed direct links to mailing list, forums etc. under the section Quick Links below.
Like the library itself, this website is also under constant development. Hence, bear with any incovenience or lack of information. Do feel free to write in your comments to my yahoo.com id sivachandra_br. If you find the library usefull/worthwhile, then do let me know as to how it is being usefull to you. I am always keen to know as to who is using the library.
You can currently contribute to libLCS in the following ways:
As libLCS is free software, all contributions will be voluntary. Contributors will not be provided with monetary compensation except in special cases.