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2.1 Why a C++ library for logic circuit simulation

There are many HDLs (Hardware Description Languages) and HVLs (Hardware Verification Languages) currently in use. Among the HDLs, Verilog is the most common language of choice. Among HVLs, the Open Vera language is fast becoming a language of choice. SystemVerilog, a successor of Verilog, can be used as a HDL (Verilog is a subset of SystemVerilog) as well as a HVL. Though these languanges are easy to use, they are all evolving to incorporate features which other general purpose object-oriented languages like C++ already possess. Hence, it is natural to ask wether a language like C++ can be used effectively as a HDL. The answer to this question is exactly what libLCS is trying to seek.

It is said that every library (in whatever base language it may have been developed in) introduces another sublanguage (such a sublanguage is usually reffered to as an API) of its own. Hence, if a C++ library can be so designed that the new sublanguage it introduces is as intuitive and as powerfull as a HDL, then the answer to the question raised in the above paragraph is an emphatic "yes". libLCS is being designed and developed to verify if it really is a "yes". The aim is to be as intuitive and powerfull as the Verilog HDL.

(A C++ API called SystemC, standardised by the IEEE, can already be used for hardware simulation and verification. However, this API is not very intiutive for hardware description.)

Another natural question which one can ask is, "Why only C++? Why not Java?" It is simply because of the operator overloading feature of C++ makes it more flexible, and hence more likely to aid in desiging an intiutive sublanguage/API for hardware description.