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- A Logic Circuit Simulation Library in C++ |
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- A Logic Circuit Simulation Library in C++ |
In a shift register, we cannot use ideal flipflops which have a zero delay. This is because, if zero delay is allowed, then the input will get bit-shifted through all the flipflops at every clock pulse! Hence, to avoid this, we will build our 4-bit shift register using D-flipsflops with which have a propogation delay of 1 system time unit. Also, we will make use of one of the counter output bits from this example as the input bit stream for our shift register. The complete circuit diagram is as shown below.
The following is the program to simulate the above circuit.
#include <iostream> #include <lcs/bus.h> #include <lcs/not.h> #include <lcs/clock.h> #include <lcs/simul.h> #include <lcs/changeMonitor.h> #include <lcs/dflipflop.h> using namespace lcs; using namespace std; int main(void) { Bus<> q0(0), q1(0), q2(0), q3(0), d0, d1, d2, d3, sr0(0), sr1(0), sr2(0), sr3(0); Clock clk = Clock::getClock(); Not<> n1(d0, q0), n2(d1, q1), n3(d2, q2), n4(d3, q3); DFlipFlop<> ff1(q0, d0, clk), ff2(q1, d1, q0), ff3(q2, d2, q1), ff4(q3, d3, q2); // Initialise the D-flipflop modules of the shift register with // a delay parameter value of 1 system time unit. DFlipFlop<POS_EDGE, 1> ff5(sr0, d1, clk), ff6(sr1, sr0, clk), ff7(sr2, sr1, clk), ff8(sr3, sr2, clk); ChangeMonitor<4> count(d0*d1*d2*d3, string("Count")); ChangeMonitor<4> sr(sr0*sr1*sr2*sr3, string("Shift Register")); Simulation::setStopTime(4000); Simulation::start(); Simulation::terminate(); return 0; }
When the above code is compiled and run, the following output is obtained.
At time: 0, Count: 1111 At time: 0, Shift Register: 0000 At time: 100, Count: 0000 At time: 300, Count: 0001 At time: 500, Count: 0010 At time: 501, Shift Register: 0001 At time: 700, Count: 0011 At time: 701, Shift Register: 0011 At time: 900, Count: 0100 At time: 901, Shift Register: 0110 At time: 1100, Count: 0101 At time: 1101, Shift Register: 1100 At time: 1300, Count: 0110 At time: 1301, Shift Register: 1001 At time: 1500, Count: 0111 At time: 1501, Shift Register: 0011 At time: 1700, Count: 1000 At time: 1701, Shift Register: 0110 At time: 1900, Count: 1001 At time: 1901, Shift Register: 1100 At time: 2100, Count: 1010 At time: 2101, Shift Register: 1001 At time: 2300, Count: 1011 At time: 2301, Shift Register: 0011 At time: 2500, Count: 1100 At time: 2501, Shift Register: 0110 At time: 2700, Count: 1101 At time: 2701, Shift Register: 1100 At time: 2900, Count: 1110 At time: 2901, Shift Register: 1001 At time: 3100, Count: 1111 At time: 3101, Shift Register: 0011 At time: 3300, Count: 0000 At time: 3301, Shift Register: 0110 At time: 3500, Count: 0001 At time: 3501, Shift Register: 1100 At time: 3700, Count: 0010 At time: 3701, Shift Register: 1001 At time: 3900, Count: 0011 At time: 3901, Shift Register: 0011
