libLCS - A Logic Circuit Simulation Library in C++

This example illustrates the propogation delay through the off-the-shelf AND gates provided in libLCS. Two AND gates, one with delay more than the clock pulse width, and the other with delay less than the clock pulse width are initialised. The program is as follows.

#include <lcs/and.h>
#include <lcs/simul.h>
#include <lcs/tester.h>
#include <lcs/changeMonitor.h>

using namespace lcs;

int main()
{
    Bus<1> a, b, s1, s2;
    Clock::setPulseWidth(5);

    // Initialising an AND gate with a propogation delay of 
    // three system time units. This delay is less than the 
    // pulse width of the clock signal.
    And<2, 3> andGate1(s1, (a,b));

    // Initialising an AND gate with a propogation delay of 
    // seven system time units. This delay is more than the 
    // pulse width of the clock signal.
    And<2, 7> andGate2(s2, (a,b));

    // Initialising change monitors to monitor the output of
    // the two AND gates.
    ChangeMonitor<> output1(s1, "Output 1");
    ChangeMonitor<> output2(s2, "Output 2");

    // Initialising a tester object to feed input to the above
    // AND gates at every change in clock state.
    Tester<2> tester((a,b));

    Simulation::setStopTime(1000);
    Simulation::start();

    return 0;
}

- A Logic Circuit Simulation Library in C++

(libLCS Example) Delay Example - 2