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- A Logic Circuit Simulation Library in C++ |
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- A Logic Circuit Simulation Library in C++ |
As was discussed in the section Building Custom Modules, a functional module has to lock all of its output busses by passing the this argument to the function lcs::Bus::lock. This function requires a second parameter as well, whose default value is 0. This parameter indicates the delay with which the line states of the bus have to be set after an assignment. ie., when a module tries to set the lines of a bus through an assignment, the line states will change after a certain delay (in system time units) specified by the second parameter to the function lcs::Bus::lock. Though this delay might feel like an assignment delay, it actually to models input to output propogation delays. In an AND gate module for example, if an assignment delay of 5 system units is set for the output bus, a change in state of one of the AND gate input lines will lead to a corresponding change in the output only after 5 system time units. Such a delay would then feel as an input to output propogation delay rather than as an assignment delay.
The delays as facilitated by the lcs::Bus::lock function can also be used to model something similar to (but not exactly) pin-to-pin delays. This is possible if a module has more than one output busses. Different delays can be set for each of the output busses. These delays, in a way but not exactly, simulate pin-to-pin delays.
NOTE: Starting with libLCS-0.0.34, the delay facility discussed above simulates inertial delays.
SEE: See the examples section for examples which illustrate the propogation delay in logic gates.
