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- A Logic Circuit Simulation Library in C++ |
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- A Logic Circuit Simulation Library in C++ |
As was discussed in the section Building Custom Modules, the output busses of a functional module have to be of type lcs::Bus. One can set assignment delays to busses of type lcs::Bus. This is done using the function lcs::Bus::setAssDelay. Though this delay is an assignment delay, it can actually be used to model input to output propogation delays of modules. In an AND gate module for example, if an assignment delay of 5 system units is set for the output bus, a change in state of one of the AND gate input lines will lead to a corresponding change in the output only after 5 system time units. Such a delay would then feel as an input to output propogation delay rather than as an assignment delay. A call to the lcs::Bus::setAssDelay function should be made in the constructor of the module class. When and where exactly in the constructor should a call to this function be made is explained here.
The delays, as facilitated by the lcs::Bus::setAssDelay function, can also be used to model something similar to (but not exactly) pin-to-pin delays. This is possible if a module has more than one output busses. Different delays can be set for each of the output busses. These delays, in a way but not exactly, simulate pin-to-pin delays.
NOTE: Starting with libLCS-0.0.34, the delay facility discussed above simulates inertial delays.
SEE: See the examples section for examples which illustrate the propogation delay in logic gates.
