libLCS - A Logic Circuit Simulation Library in C++

This example illustrates the propogation delay through the off-the-shelf OR gates provided in libLCS. Two OR gates, one with delay more than the clock pulse width, and the other with delay less than the clock pulse width are initialised. The program is as follows.

#include <lcs/or.h>
#include <lcs/simul.h>
#include <lcs/tester.h>
#include <lcs/changeMonitor.h>

using namespace lcs;

int main()
{
    Bus<1> a, b, s1, s2;
    Clock::setPulseWidth(5);

    // Initialising an OR gate with a propogation delay of 
    // three system time units. This delay is less than the 
    // pulse width of the clock signal.
    Or<2, 3> orGate2(s1, (a,b));

    // Initialising an OR gate with a propogation delay of 
    // seven system time units. This delay is more than the 
    // pulse width of the clock signal.
    Or<2, 7> orGate1(s2, (a,b));

    // Initialising change monitors to monitor the output of
    // the two OR gates.
    ChangeMonitor<> output1(s1, "Output1", DUMP_ON);
    ChangeMonitor<> output2(s2, "Output2", DUMP_ON);

    Tester<2> tester((a,b));

    Simulation::setStopTime(50);
    Simulation::start();

    return 0;
}

At time: 3,     Output 1: 0
At time: 7,     Output 2: 0
At time: 13,    Output 1: 1
At time: 17,    Output 2: 1

- A Logic Circuit Simulation Library in C++

(libLCS Example) Delay Example - 3