3.3 Logic Gates

Logic gates are provided as primitives in Verilog. In libLCS, all circuit elements which have well defined sets of inputs and outputs are called Modules. Since logic gates also have well defined inputs and outputs, they are also treated as modules.

3.3.1 The logic gate class templates

All logic gate modules in libLCS (except the NOT gate module) are provided as class templates requiring two template parameters. The first template argument denotes the number of inputs to the gate, and the second template parameter denotes the input to output propogation delay of the gate. Since a NOT gate can have only one input, it is provided as a class template taking only one template parameter which represents the input to output propogation delay of the NOT gate. The following is the list of all logic gate class templates provided in libLCS.

1. The AND gate class template:

             template<unsigned int width = 1, unsigned int delay = 0>
             class And;
        

2. The OR gate class template:

             template<unsigned int width = 1, unsigned int delay = 0>
             class Or;
        

3. The NAND gate class template:

             template<unsigned int width = 1, unsigned int delay = 0>
             class Nand;
        

4. The NOR gate class template:

             template<unsigned int width = 1, unsigned int delay = 0>
             class Nor;
        

5. The XOR gate class template:

             template<unsigned int width = 1, unsigned int delay = 0>
             class Xor;
        

6. The NOT gate class template:

             template<unsigned int delay = 0>
             class Not;
        

3.3.2 The logic gate constructors

All logic gate module constructors require two arguments. The first argument represents the output bus, and the second argument represents the input bus. For example, if one is desirous of initialising a 5 input XOR gate with zero propogation delay, then he/she should do the following.

     
     Bus<5> inBus;
     Bus<1> outBus;
     
     Xor<5> xorGate(outBus, inBus); // The template parameter for delay is not explicitly mentioned.
                                    // Hence, the default value of zero is implied.
     

3.3.3 Logic gate header files

Following is a list of all the logic gate modules and the corresponding header file in which they are defined.

1. AND gate module

             lcs/and.h
        

2. OR gate module

             lcs/or.h
        

3. NAND gate module

             lcs/nand.h
        

4. NOR gate module

             lcs/nor.h
        

5. NOT gate module

             lcs/not.h
        

6. XOR gate module

             lcs/xor.h