In the Verilog hardware description language, modules are omni present and atleast one module has to be defined to perform even the simplest of simulations. In contrast, libLCS does not require that a user has to define a module to perform a simulation. As presented in the chapter Introduction to libLCS, one can use the off-the-shelf logic gates to build his/her system and perform a simulation. However, such an approach is suitable only for building small and simple systems. As the system grows in size and complexity, building it using the off-the-shelf logic gates, flip-flops and other utility modules gets very laborious and error prone. One should follow a top-down design approach and build modules which consist of other simpler sub modules. Moreover, as the system gets complex, simulating/testing the under lying algorithm becomes more important than the actual gate-level circuit. For this, one would need to build modules which are functional equivalents of the actual gate-level circuit. Such an abstraction of a system is called as behavioral modelling.
libLCS facilitates a user to build his/her own modules. These user defined modules can consist of other modules and/or behavioral models. In this chapter three example module descriptions are used to explains the techniques, steps and libLCS constructs which one should use in order to build their own modules. The material presented will be best understood if the sections presenting these example modules are read in the following order.