- A Logic Circuit Simulation Library in C++ |
INPUT | lcs::Not< delay > | [static] |
Module(void) | lcs::Module | [inline] |
Not(const Bus< 1 > &output, const InputBus< 1 > &input) | lcs::Not< delay > | |
onNegEdge(int portId) | lcs::Module | [inline, virtual] |
onPosEdge(int portId) | lcs::Module | [inline, virtual] |
onStateChange(int portId) | lcs::Not< delay > | [virtual] |
OUTPUT | lcs::Not< delay > | [static] |
~Module() | lcs::Module | [inline, virtual] |
~Not() | lcs::Not< delay > | [virtual] |