- A Logic Circuit Simulation Library in C++

lcs::Not< delay > Class Template Reference

#include <not.h>

Inheritance diagram for lcs::Not< delay >:

List of all members.

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Detailed Description

template<unsigned int delay = 0>
class lcs::Not< delay >

A class which encapsulates a logical NOT gate. Unlike most other gates in libLCS, the NOT gate can only take a single line input bus. The template parameter delay indicates the propogation delay from the input to the output of the NOT gate.

Public Member Functions
	Not (const Bus< 1 > &output, const InputBus< 1 > &input)
virtual	~Not ()
virtual void	onStateChange (int portId)
Static Public Attributes
static const int	INPUT = 0
static const int	OUTPUT = 1

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Constructor & Destructor Documentation

template<unsigned int delay>

lcs::Not< delay >::Not	(	const Bus< 1 > &	output,
		const InputBus< 1 > &	input
	)

The only meaningfull constructor for the class. A default constructor is not explicitly provided. Moreover, the one synthesized by the compiler is practically useless.

Parameters:

	output	The single line output bus of the gate.
	input	The multiline input bus to the gate.
	width	The number of lines in the input bus.

template<unsigned int delay>

lcs::Not< delay >::~Not

(

)

[virtual]

Destructor.

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Member Function Documentation

template<unsigned int delay>

void lcs::Not< delay >::onStateChange

(

int

portId

)

[virtual]

Propogates the input data line states to the output. This function is called by the input bus line to notify the gate of a lcs::LINE_STATE_CHANGE event. When notified, a NOT operation is performed on the line state of the data line of the input bus and the result is propogated to the single line output bus.

Reimplemented from lcs::Module.

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Member Data Documentation

template<unsigned int delay = 0>

const int lcs::Not< delay >::INPUT = 0 [static]

A constant integer which denotes the port id for the input port/bus.

template<unsigned int delay = 0>

const int lcs::Not< delay >::OUTPUT = 1 [static]

A constant integer which denotes the port id for the output bus/port.

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Copyright © 2006, 2007 Siva Chandra