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- A Logic Circuit Simulation Library in C++ |
#include <freqdiv.h>
Inheritance diagram for lcs::FrequencyDivider< factor >:
Public Member Functions | |
FrequencyDivider (const Bus< 1 > &output, const InputBus< 1 > &input) | |
virtual | ~FrequencyDivider () |
virtual void | onPosEdge (int portId) |
lcs::FrequencyDivider< factor >::FrequencyDivider | ( | const Bus< 1 > & | output, | |
const InputBus< 1 > & | input | |||
) |
The only usefull constructor for the class. The default constructor, if synthesised by the compiler, is practically useless.
output | The bus of the module. | |
input | The input bus of the module. |
virtual lcs::FrequencyDivider< factor >::~FrequencyDivider | ( | ) | [inline, virtual] |
Destructor.
void lcs::FrequencyDivider< factor >::onPosEdge | ( | int | portId | ) | [virtual] |
Function which toggles the output line state at the suitable positive edge. A user of libLCS will never need to use this function directly/explicitly.
Reimplemented from lcs::Module.