- A Logic Circuit Simulation Library in C++ |
Buffer(const Bus< lines > &output, const InputBus< lines > &input) | lcs::Buffer< lines, delay > | |
Module(void) | lcs::Module | [inline] |
onNegEdge(int portId) | lcs::Module | [inline, virtual] |
onPosEdge(int portId) | lcs::Module | [inline, virtual] |
onStateChange(int portId) | lcs::Buffer< lines, delay > | [virtual] |
~Buffer() | lcs::Buffer< lines, delay > | |
~Module() | lcs::Module | [inline, virtual] |