libLCS - A Logic Circuit Simulation Library in C++

As was discussed in the section Building Custom Modules, the output busses of a functional module have to be of type lcs::Bus. This is because, lcs::Bus objects are read-write objects which allow the user to set their line states using overloaded assignment operators. Along with setting the line states, the user can also specify an assignment delay. Examples of incorporating such assignment delays are as follows.

lcs::Bus<3> b1;
b1[1] = (5, lcs::HIGH); // Setting the line state of the 2nd line 
                        // of the bus b1 to lcs::HIGH with a delay
                        // of 5 system time units. Note the 
                        // neccessary enclosing parentheses around
                        // the delay-state pair.

lcs::Bus<3> b2(0), b3(5);
b2[1] = (5, b3[1] | b2[0]); // Setting the line state of the 2nd line 
                            // of the bus b1 to the result of an 
                            // expression with an assignment delay
                            // of 5 system time units. Note the 
                            // neccessary enclosing parentheses around
                            // the delay-expression pair.

lcs::Bus<3> b4;
b4 = (5, lcs::HIGH); // Setting the line states of all the lines 
                     // of the bus b4 to lcs::HIGH with an
                     // assignment delay of 5 system time units. 
                     // Note the neccessary enclosing parentheses 
                     // around the delay-state pair.

lcs::Bus<3> b5(0), b6(5), b7(7);
b5 = (5, b6 ^ b7); // Setting the line states of the bus b4 to 
                   // the result of an expression with an assignment
                   // delay of 5 system time units. Note the 
                   // neccessary enclosing parentheses around the 
                   // delay-expression pair.

Though the delay (as incorporated in the above examples) is an assignment delay, it can actually be used to model input to output propogation delays in modules. In an AND gate module for example, if an assignment delay of 5 system units is used for setting the output bus line state, a change in state of one of the AND gate input lines will lead to a corresponding change in the output only after 5 system time units. Such a delay would then feel as an input to output propogation delay rather than as an assignment delay.

The delays, as incorporated in the above examples, can also be used to model something similar to (but not exactly) pin-to-pin delays. Different delays can be used for setting the lines of the output busses. These different delays, in a way but not exactly, simulate pin-to-pin delays.

NOTE: In older versions of libLCS, the delay feature was inertial. However, it led to unknown behaviour when a user used different assignment delays for one single bus or line. Only one single assignment delay had to be used for any given line to avoid it. This drawback has been eliminated starting with libLCS-0.0.49.1. However, the delays are are not inertial anymore. The inertial delay feature is currently suspended and will be back in a future release when an elegant way to incorporate it is found.

SEE: See the examples section to find examples which illustrate the propogation delay in logic gates.

- A Logic Circuit Simulation Library in C++

Incorporating delays into functional modules