- A Logic Circuit Simulation Library in C++

(libLCS Example) 1-bit Fulladder with continuous assignments on bit-selects

The following program simulates a 1-bit fulladder using continuous assignments on bit-selects. The 3-line input bus is represented by the variable IN, and corresponds to the 2 single bit inputs and the carry input. The 2-line sum output is represented by the variable S.

#include <lcs/lcs.h>

using namespace lcs;
using namespace std;

int main(void)
    Bus<3> IN;
    Bus<2> S;

    // Continuous assignment statements to generate
    // the sum and carry outputs. The template parameters
    // indicate the assignment delay. We have used 0
    // delay here.
    S[0].cass<0>(IN[0]&~IN[1]&~IN[2] | ~IN[0]&IN[1]&~IN[2] | ~IN[0]&~IN[1]&IN[2] | IN[0]&IN[1]&IN[2]);
    S[1].cass<0>(IN[0]&IN[1]&~IN[2] | IN[0]&~IN[1]&IN[2] | ~IN[0]&IN[1]&IN[2] | IN[0]&IN[1]&IN[2]);

    ChangeMonitor<3> inputMonitor(IN, "Input", DUMP_ON);
    ChangeMonitor<2> outputMonitor(S, "Sum", DUMP_ON);

    Tester<3> tester(IN);


    return 0;

When the above program is compiled and run, the following is displayed on the standard output.

At time: 0,	Input: 000
At time: 0,	Sum: 00
At time: 200,	Input: 001
At time: 200,	Sum: 01
At time: 300,	Input: 010
At time: 400,	Input: 011
At time: 400,	Sum: 10
At time: 500,	Input: 100
At time: 500,	Sum: 01
At time: 600,	Input: 101
At time: 600,	Sum: 10
At time: 700,	Input: 110
At time: 800,	Input: 111
At time: 800,	Sum: 11

The corresponding GTKWave plot for the above simulation is as follows.


Copyright © 2006, 2007 Siva Chandra