- A Logic Circuit Simulation Library in C++

lcs::Register< bits, edgeType, delay > Member List

This is the complete list of members for lcs::Register< bits, edgeType, delay >, including all inherited members.

Module(void)	lcs::Module	`[inline]`
onNegEdge(int portId)	lcs::Register< bits, edgeType, delay >	`[inline, virtual]`
onPosEdge(int portId)	lcs::Register< bits, edgeType, delay >	`[inline, virtual]`
onStateChange(int portId)	lcs::Module	`[inline, virtual]`
operator[](const int &i)	lcs::Register< bits, edgeType, delay >	`[inline]`
Register(const Bus< bits > &out, const InputBus< bits > &in, const InputBus< 1 > &clk)	lcs::Register< bits, edgeType, delay >
~Module()	lcs::Module	`[inline, virtual]`
~Register()	lcs::Register< bits, edgeType, delay >	`[virtual]`