Module(void) | lcs::Module | [inline] |
onNegEdge(int portId) | lcs::ShiftReg< bits, edgeType, shift, delay > | [inline, virtual] |
onPosEdge(int portId) | lcs::ShiftReg< bits, edgeType, shift, delay > | [inline, virtual] |
onStateChange(int portId) | lcs::Module | [inline, virtual] |
operator[](const int &i) | lcs::ShiftReg< bits, edgeType, shift, delay > | [inline] |
ShiftReg(const Bus< bits > &out, const InputBus< 1 > &in, const InputBus< 1 > &clk) | lcs::ShiftReg< bits, edgeType, shift, delay > | |
~Module() | lcs::Module | [inline, virtual] |
~ShiftReg() | lcs::ShiftReg< bits, edgeType, shift, delay > | [virtual] |